H.264 DECODER SOC ARCHITECTURE BASED ON CO-PROCESSOR

被引：0

作者：

Zhang, ZhiXun ^{[1
]}

Wang, Juan ^{[1
]}

Wang, Yongdong ^{[2
]}

机构：

[1] Lanzhou Inst Technol, Dept Software Engn, Lanzhou 730050, Peoples R China

[2] AMD SRDC, Shanghai 200000, Peoples R China

来源：

FRONTIERS OF MANUFACTURING SCIENCE AND MEASURING TECHNOLOGY III, PTS 1-3 | 2013年 / 401卷

关键词：

H.264; Co-processor; SOC;

D O I：

10.4028/www.scientific.net/AMM.401-403.1879

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

This paper presents the architecture and implementation of a H.264 decoder SOC system. The SOC system has mixed hardware arithmetic unit and software instruction based on co-processors, which are designed by analyzing the major arithmetic units of H.264 decoder. The co-processor approach can meet certain performance requirement with high scalability, which can be easy for system upgrade and expansion in the future. The verification result shows that the SOC system can speed up H.264 decoding process by saving more than 75% of the decoding time.

引用

页码：1879 / +

页数：3

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