A New VLSI Architecture Implementation for H.264 Decoder

被引：0
|
作者：
Zhang, Chi [1 ]
Liu, Bu-ming [1 ]
机构：
[1] Univ Elect Sci & Technol China, Sch Microelect & Solid State Elect, Chengdu 610054, Sichuan, Peoples R China
来源：
2009 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLUMES I & II | 2009年
关键词：
D O I：
10.1109/ICCCAS.2009.5250348
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
in this paper, a new flexible VLSI architecture of H.264/AVC decoder is presented. The proposed design implementation can get a good performance result as fully pipelined construction.
引用
收藏
页码：1057 / 1058
页数：2
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