Investigation of Design and Material Optimization on High bandwidth Package on Package

High bandwidth Package on Package (HBPoP) had be well used which replaced FCMAPPOP in high-end mobile products with its advantages of wide 110 counts, high performance and the better integration between application processor and stacked memory packages. The structure of HBPoP is utilized flip-chip technology with ball grid array (BGA) balls on the bottom package and connect top DRAM package with substrate interposer (SI). In order to well mount with top memory package, the package warpage control is an essential issue since DRAM package is produced from various suppliers. Hence HBPOP has strict specification to control warpage performance from room temperature to reflow temperature. However, the coefficient of thermal expansion (CTE) mismatch between different materials causes serious warpage issue and affects yield of memory stacking in thermal loading. This study adopted finite element method and consider substrate trace layout to assess the warpage performance and validate with measurement results to build up a robust prediction model. Several geometrical and material factors were investigated, including: interposer pattern design, SI and bottom substrate thickness, SI core type, DAF size...etc. Consequently, high CTE SI core, small DAF size, thin bottom substrate and thick SI copper thickness have significant influence for better warpage performance.