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Technologies for 3D Wafer Level Heterogeneous Integration

被引：28
|
作者：
Wolf, M. J. [1 ]
Ramm, P. [2 ]
Klumpp, A. [2 ]
Reichl, H. [1 ]
机构：
[1] Fraunhofer IZM, Berlin, Germany
[2] Fraunhofer IZM, Munich, Germany
来源：
DTIP 2008: SYMPOSIUM ON DESIGN, TEST, INTEGRATION AND PACKAGING OF MEMS/MOEMS | 2008年
关键词：
D O I：
10.1109/DTIP.2008.4752966
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
integration is a fast growing field that encompasses different types of technologies. The paper addresses one of the most promising technology which uses Through Silicon Vias (TSV) for interconnecting stacked devices on wafer level to perform high density interconnects with a good electrical performance at the smallest form factor for 3D architectures. Fraunhofer IZM has developed a post front-end 3D integration process which allows stacking of functional and tested FE-devices e.g. sensors, ASICs on wafer level as well as a technology portfolio for passive silicon interposer with redistribution layers and TSV.
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收藏
页码：123 / +
页数：2
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