A methodology for optimum delay, skew, and power performances in an FPGA clock network

被引：0
|
作者：
Sulaiman, Mohd S. [1 ]
机构：
[1] Multimedia Univ, Fac Engn, Selangor 63100, Malaysia
来源：
INFORMACIJE MIDEM-JOURNAL OF MICROELECTRONICS ELECTRONIC COMPONENTS AND MATERIALS | 2006年 / 36卷 / 02期
关键词：
FPGA clock network; high performance; IC design; low power design; CMOS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A methodology for FPGA clock network optimisation is presented. The algorithms for optimisation of clock skew, delay, and power considering slew rate constraint for an FPGA fixed-clock network are implemented and verified on SX 32 FPGA chip. Measurements indicated a 60% reduction in clock slew rate and a 22% improvement in power dissipation when compared to the results of the initial, un-optimised chip.
引用
收藏
页码：85 / 90
页数：6
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