Design and implementation of clock network for nanometer FPGA

被引：0

作者：

Li, Lei ^{[1
]}

Lai, Jinmei ^{[1
]}

机构：

[1] Fudan Univ, Dept Microelect, ASIC & Syst State Key Lab, Shanghai 201203, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2015年 / 12卷 / 05期

关键词：

clock network; FPGA; skew; latency; DAU; BUFFER INSERTION; SKEW;

D O I：

10.1587/elex.12.20141180

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper is committed to design and implement FPGA clock network with overall considerations of speed and power in circuit design perspective. Mixed structure MUX, programmable delay adjustment unit and power-down bit strategies are presented to optimize its latency, skew and power. This clock network is implemented with 65 nm process and applied to own-designed FPGA. Test results indicate 21.7% reduction in latency and 54.5% reduction in skew, compared to counterpart FPGA device, while maintaining lower power consumption.

引用

页数：10

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