Low power-delay-product dynamic CMOS circuit design techniques

被引：11
|
作者：
Xue, H. [1 ]
Ren, S. [1 ]
机构：
[1] Wright State Univ, Dayton, OH 45435 USA
来源：
ELECTRONICS LETTERS | 2017年 / 53卷 / 05期
关键词：
low-power electronics; delay circuits; CMOS integrated circuits; integrated circuit design; PDP dynamic CMOS circuit design techniques; low power-delay-product circuit design techniques; dynamic circuit delay improvement; non-inverted dynamic benchmarks; inverted dynamic benchmarks; voltage; 1; 2; V; size; 90; nm;
D O I：
10.1049/el.2016.4173
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Two low power-delay-product (PDP) dynamic CMOS circuit design techniques are proposed. The techniques can simply modify existing dynamic CMOS designs to improve dynamic circuit delay and PDP. Conventional benchmark circuits and the modified circuits using the proposed techniques are implemented in 90 nm CMOS technology with a 1.2 V power supply. Simulation results indicate that the proposed techniques can improve circuit PDP by 19.2 and 61.9% in two non-inverted dynamic benchmarks, respectively, and 6.2 and 33.72% in two inverted dynamic benchmarks, respectively.
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页码：302 / 303
页数：2
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