共 50 条
- [21] DLV (Deep low voltage): Circuits and devices INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2005, 3728 : 748 - 748
- [23] Sizing of Dual-VT Gates for Sub-VT Circuits 2012 IEEE SUBTHRESHOLD MICROELECTRONICS CONFERENCE (SUBVT), 2012,
- [24] SCDNDTDL: a technique for designing low-power domino circuits in FinFET technology Journal of Computational Electronics, 2020, 19 : 1249 - 1267
- [25] IDD waveforms analysis for testing of domino and low voltage static CMOS circuits PROCEEDINGS OF THE 8TH GREAT LAKES SYMPOSIUM ON VLSI, 1998, : 243 - 248
- [26] A Low-Power Management Technique for High-Performance Domino Circuits 2011 16TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2011,
- [28] Low-power Dual Vth Pseudo dual Vdd domino circuits SBCCI2004:17TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS, 2004, : 273 - 277
- [29] Design of low-power domino circuits using multiple supply voltages ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS, 2001, : 711 - 714
- [30] Delay variation tolerance for domino circuits ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 2006, : 354 - 359