A High Performance Modulo 2n+1 Squarer Design Based on Carbon Nanotube Technology

In this paper, a design of high performance modulo 2(n)+1 squarer is proposed. The primary improvement comes from the algorithm, circuit implementation, and implementation technology. For the algorithm, the partial product matrix reconstruction is optimized to achieve a larger range of input and fewer operation steps. The modified Wallace tree is employed to compress the partial product in each column. For circuit implementation, full adders in traditional structure are replaced by 3: 2 compressors. The sparse-tree based inverted End-Carry-Around (ECA) modulo 2(n) adder is utilized to implement the final addition stage. The proposed design is demonstrated a much better performance in terms of delay, power, and area comparing with existing design. To assess the advantage of CNT device, the same circuit is designed using CNT technology. The proposed design shows that the critical path delay and rise time of modulo 2(8)+1 squarer on CNT technology is 13.6 times and 9.3 times better than that of CMOS technology, respectively. The power consumption is improved about 4 times with much better tolerance against the process, voltage, and temperature (PVT) variation compared with the CMOS counterpart.