Fast modulo 2n-1 and 2n+1 adder using carry-chain on FPGA

被引：0

作者：

Didier, Laurent-Stephane ^{[1
]}

Jaulmes, Luc ^{[2
]}

机构：

[1] Univ Toulon & Var, Lab IMATH, La Garde, France

[2] Univ Politecn Cataluna, CNS, Barcelona Supercomp Ctr, Barcelona, Spain

来源：

2013 ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS | 2013年

关键词：

Modular adder; carry-chain; FPGA; RNS; 2(n)-1 and 2(n)+1 moduli; MULTIPLICATION; IMPLEMENTATION; DESIGN;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Modular addition is a widely used operation in Residue Number System applications. Specific sets of moduli allow fast RNS operations such as binary conversions and multiplications. Most of them use modulo 2(n) - 1 and 2(n) + 1 additions. This paper presents four fast and small architectures for these specific moduli targeting modern FPGAs with fast carry chains. The use of this arithmetic dedicated feature allows fast and small modular adders. Our modulo 2(n) - 1 adders have a single zero representation. Our modulo 2(n) + 1 adders are designed for binary and diminished-one representation with and without zero value management.

引用

页码：1155 / 1159

页数：5

共 50 条

[1] Area-Power Efficient Modulo 2n-1 and Modulo 2n+1 Multipliers for {2n-1, 2n, 2n+1} Based RNS
Muralidharan, Ramya
Chang, Chip-Hong
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2012, 59 (10) : 2263 - 2274
[2] On Modulo 2n+1 Adder Design
Vergos, Haridimos T.
Dimitrakopoulos, Giorgos
IEEE TRANSACTIONS ON COMPUTERS, 2012, 61 (02) : 173 - 186
[3] Efficient VLSI design of modulo 2n-1 adder using hybrid carry selection
Lin, Su-Hon
Sheu, Ming-Hwa
Wang, Kuang-Hui
Zhu, Jun-Jie
Chen, Si-Ying
2007 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS, VOLS 1 AND 2, 2007, : 142 - 145
[4] Efficient methods in converting to modulo 2n+1 and 2n-1
Manochehri, Kooroush
Pourmozafari, Saadat
Sadeghian, Babak
THIRD INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY: NEW GENERATIONS, PROCEEDINGS, 2006, : 178 - +
[5] A Logarithmic Depth Quantum Carry-Lookahead Modulo (2n-1) Adder
Gaur, Bhaskar
Munoz-Coreas, Edgard
Thapliyal, Himanshu
PROCEEDINGS OF THE GREAT LAKES SYMPOSIUM ON VLSI 2023, GLSVLSI 2023, 2023, : 125 - 130
[6] Efficient modulo 2n+1 adder architectures
Vergos, H. T.
Efstathiou, C.
INTEGRATION-THE VLSI JOURNAL, 2009, 42 (02) : 149 - 157
[7] Modulo deflation in (2n+1,2n, 2n-1) converters
Bi, S
Wang, W
Al-Khalili, A
2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2004, : 429 - 432
[8] Area-time efficient modulo 2n-1 adder design using hybrid carry selection
Lin, Su-Hon
Shew, Ming-Hwa
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2008, E91D (02): : 361 - 362
[9] Fast hard multiple generators for radix-8 Booth encoded modulo 2n-1 and modulo 2n+1 multipliers
Muralidharan, Ramya
Chang, Chip-Hong
2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 717 - 720
[10] Design and Simulation of Diminished-One Modulo 2n+1 Adder Using Circular Carry Selection
Singh, Ruchi
Mishra, R. A.
WORLD CONGRESS ON ENGINEERING, WCE 2011, VOL II, 2011, : 1515 - 1518

← 1 2 3 4 5 →