共 50 条
- [31] A 0.6V 50-to-145MHz PVT Tolerant Digital PLL with DCO-Dedicated ΔΣ LDO and Temperature Compensation Circuits in 65nm CMOS 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2017,
- [32] A 0.55V 100MHz ADPLL with ΔΣ LDO and Relaxation DCO in 65nm CMOS 2015 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT), 2015, : 190 - 192
- [33] A Programmable Gain Dynamic Residue Amplifier in 65nm CMOS 2023 ARGENTINE CONFERENCE ON ELECTRONICS, CAE, 2023, : 52 - 56
- [34] A Spatial-LDI Δ-Σ LNA Design in 65nm CMOS 2024 INTERNATIONAL APPLIED COMPUTATIONAL ELECTROMAGNETICS SOCIETY SYMPOSIUM, ACES 2024, 2024,
- [35] Gilbert Cell Mixer Design in 65nm CMOS Technology 2017 4TH INTERNATIONAL CONFERENCE ON ELECTRICAL AND ELECTRONIC ENGINEERING (ICEEE 2017), 2017, : 67 - 72
- [36] A Low-Noise Analog Baseband in 65nm CMOS IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010, 2010,
- [38] Radiation Tolerant SRAM Cell Design in 65nm Technology JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2021, 37 (02): : 255 - 262
- [39] High performance CMOS variability in the 65nm regime and beyond 2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, : 569 - 571
- [40] A 70 and 210 GHz LO generator in 65nm CMOS PROCEEDINGS OF THE 2012 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY (RFIT), 2012, : 195 - 197