Development of design rule checker for mask generation of semiconductor devices

被引：0

作者：

Gupta, I ^{[1
]}

Pandey, RK ^{[1
]}

机构：

[1] Solid State Phys Lab, Delhi 110054, India

来源：

PROCEEDING OF THE TENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOLS I AND II | 2000年 / 3975卷

关键词：

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

A CAD tool for generation of masks of integrated devices was developed using the language AutoLisp. The software AutoCAD that provides a built in Lisp interpreter was used to develop the software Layout Editor. It was essential to verify the output of the layout editor on the basis of the design rules of the foundry. This paper discusses a few salient features of the software developed for the same. It also produces a list out of the errors, which can then be modified before sending the final design to the foundry.

引用

页码：841 / 844

页数：4

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