A fast and area efficient complementary pass-transistor logic carry-skip adder

被引：0
|
作者：
Strollo, AGM
Napoli, E
机构：
来源：
1997 21ST INTERNATIONAL CONFERENCE ON MICROELECTRONICS - PROCEEDINGS, VOLS 1 AND 2 | 1997年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A two-level carry-skip adder using complementary pass-transistor logic is presented in this paper, The proposed adder is fast, area efficient and highly modular, It is compared with a two-level carry-skip adder using CMOS logic, and with a carry-lookhaed adder automatically generated with the ALLIANCE CAD tools, SPICE simulations of the circuit extracted from the layout are used to evaluate the adder delay, while switch-level simulations are used to evaluate average power dissipation.
引用
收藏
页码：701 / 704
页数：4
相关论文
共 50 条
  • [1] Performance analysis of a two-level carry-skip adder implemented in complementary pass-transistor logic
    Strollo, AGM
    Napoli, E
    MICROELECTRONICS JOURNAL, 1998, 29 (10) : 755 - 760
  • [2] Delay efficient 32-bit carry-skip adder
    Lin, Yu Shen
    Radhakrishnan, Darnu
    2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2006, : 506 - 509
  • [3] Delay Efficient 32-Bit Carry-Skip Adder
    Lin, Yu Shen
    Radhakrishnan, Damu
    VLSI DESIGN, 2008,
  • [4] 64-bit low threshold voltage high-speed conditional carry adder by complementary pass-transistor logic
    Cheng, KH
    Cheng, SW
    Liao, CY
    VLSI 2004: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS, 2004, : 233 - 236
  • [5] An Efficient Power Clock Generation Circuit for Complementary Pass-Transistor Adiabatic Logic Carry-Save Multiplier
    Ranjith, P.
    Mandal, Sushanta K.
    Nagchoudhuri, Dipankar
    2009 4TH INTERNATIONAL CONFERENCE ON COMPUTERS AND DEVICES FOR COMMUNICATION (CODEC 2009), 2009, : 92 - 95
  • [6] Performance enhancement of efficient process based on Carry-Skip Adder for IoT applications
    Bagyalakshmi, K.
    Karpagam, M.
    MICROPROCESSORS AND MICROSYSTEMS, 2020, 76
  • [7] Fault characterisation of Complementary Pass-transistor Logic circuits
    Aziz, SM
    Rashid, ABMH
    Karim, M
    2000 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS, 2000, : 80 - 84
  • [8] Area-efficient nonvolatile carry chain based on pass-transistor/atom-switch hybrid logic
    Bai, Xu
    Tsuji, Yukihide
    Sakamoto, Toshitsugu
    Morioka, Ayuka
    Miyamura, Makoto
    Tada, Munehiro
    Banno, Naoki
    Okamoto, Koichiro
    Iguchi, Noriyuki
    Hada, Hiromitsu
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2016, 55 (04)
  • [9] Partially duplicated code-disjoint carry-skip adder
    Marienfeld, D
    Ocheretnij, V
    Gössel, M
    Sogomonyan, ES
    17TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2002, : 78 - 86
  • [10] Low power adiabatic multiplier with complementary pass-transistor logic
    Hu, JP
    Xu, TF
    Lin, P
    Xia, YS
    2005 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS: VOL 1: COMMUNICATION THEORY AND SYSTEMS, 2005, : 1065 - 1069
12345