Delay efficient 32-bit carry-skip adder

被引：0

作者：

Lin, Yu Shen ^{[1
]}

Radhakrishnan, Darnu ^{[1
]}

机构：

[1] SUNY Albany, Dept Elect & Comp Engn, New Paltz, NY 12561 USA

来源：

2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3 | 2006年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper. The group generate and group propagate functions used in carry look ahead logic are used to speed up multiple stages of ripple carry adders. The optimum sizes for the skip blocks are decided by considering the critical path into account. The adder is implemented in 0.25 mu m CMOS technology at 3.3V. The simulation results showed a critical path delay of 3.4ns, which translates to a speed improvement of 18% compared to the current fastest carry skip adder.

引用

页码：506 / 509

页数：4

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