A fast and area efficient complementary pass-transistor logic carry-skip adder

被引：0
|
作者：
Strollo, AGM
Napoli, E
机构：
来源：
1997 21ST INTERNATIONAL CONFERENCE ON MICROELECTRONICS - PROCEEDINGS, VOLS 1 AND 2 | 1997年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A two-level carry-skip adder using complementary pass-transistor logic is presented in this paper, The proposed adder is fast, area efficient and highly modular, It is compared with a two-level carry-skip adder using CMOS logic, and with a carry-lookhaed adder automatically generated with the ALLIANCE CAD tools, SPICE simulations of the circuit extracted from the layout are used to evaluate the adder delay, while switch-level simulations are used to evaluate average power dissipation.
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页码：701 / 704
页数：4
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