A design of general multiplier in GF(28) and FPGA implementation

被引：1

作者：

Yang, Xiaohui ^{[1
]}

Dai, Zibin ^{[1
]}

Yu, Xuerong ^{[1
]}

Su, Jinhai ^{[1
]}

机构：

[1] PLA Informat Engn Univ, Inst Elect Technol, Zhengzhou 450004, Peoples R China

来源：

2006 1ST INTERNATIONAL SYMPOSIUM ON PERVASIVE COMPUTING AND APPLICATIONS, PROCEEDINGS | 2006年

关键词：

finite field; GF (2(8)) multiplication; FPGA;

D O I：

10.1109/SPCA.2006.297444

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

In the paper, we have introduced the theory of Generalized Multiplier in GF (2(8)). The design can be used in GF (2(8)) for arbitrary modulo polynomial. Based on the theory, we have implemented the circuit based on our design schemes, and take example in the various cipher algorithms application. Finally, we give the implementation result based on the FPGA of the family of Stratix II of Altera corporation.

引用

页码：503 / +

页数：2

共 50 条

[1] The Design and FPGA Implementation of GF(2128) Multiplier for Ghash
Huo, Jia
Shou, Guochu
Hu, Yihong
Guo, Zhigang
NSWCTC 2009: INTERNATIONAL CONFERENCE ON NETWORKS SECURITY, WIRELESS COMMUNICATIONS AND TRUSTED COMPUTING, VOL 1, PROCEEDINGS, 2009, : 554 - 557
[2] An FPGA implementation of a Montgomery multiplier over GF(2M)
Mentens, N
Örs, SB
Preneel, B
Vandewalle, J
COMPUTING AND INFORMATICS, 2004, 23 (5-6) : 487 - 499
[3] FPGA Design and Implementation of Large Integer Multiplier
Xie Xing
Huang Xinming
Sun Ling
Han Saifei
JOURNAL OF ELECTRONICS & INFORMATION TECHNOLOGY, 2019, 41 (08) : 1855 - 1860
[4] GF(q) LDPC decoder design for FPGA implementation
Sulek, Wojciech
Kucharczyk, Marcin
Dziwoki, Grzegorz
2013 IEEE CONSUMER COMMUNICATIONS AND NETWORKING CONFERENCE (CCNC), 2013, : 460 - 465
[5] FPGA implementation of an efficient multiplier over finite fields GF(2m)
García-Martínez, MA
Posada-Gómez, R
Morales-Luna, G
Rodríguez-Henríquez, F
2005 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG 2005), 2005, : 171 - 175
[6] VLSI Design of High Speed Vedic Multiplier for FPGA Implementation
Gavali, Kapil Ram
Kadam, Poonam
PROCEEDINGS OF 2ND IEEE INTERNATIONAL CONFERENCE ON ENGINEERING & TECHNOLOGY ICETECH-2016, 2016, : 936 - 939
[7] Design and Implementation of Energy Efficient Vedic Multiplier using FPGA
Patil, Hemangi P.
Sawant, S. D.
2015 IEEE INTERNATIONAL CONFERENCE ON INFORMATION PROCESSING (ICIP), 2015, : 206 - 210
[8] Design and FPGA Implementation of Matrix Multiplier Using DEMUX-RCA-Based Vedic Multiplier
Kumar, Balivada Yashwant
Kharwar, Saurabh
Singh, Sangeeta
Mohammed, Mustafa K. A.
Dauwed, Mohammed
PROCEEDINGS OF THE 2ND INTERNATIONAL CONFERENCE ON EMERGING TECHNOLOGIES AND INTELLIGENT SYSTEMS, ICETIS 2022, VOL 2, 2023, 573 : 216 - 224
[9] Revisiting FPGA Implementation of Montgomery Multiplier in Redundant Number System for Efficient ECG Applications in GF(p)
Roy, Debapriya Basu
Mukhopadhyay, Debdeep
2018 28TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL), 2018, : 323 - 326
[10] Design and Implementation of Adders and Multiplier in FPGA Using ChipScope: A Performance Improvement
Shirol, Suhas B.
Ramakrishna, S.
Shettar, Rajashekar B.
INFORMATION AND COMMUNICATION TECHNOLOGY FOR COMPETITIVE STRATEGIES, 2019, 40 : 11 - 19

← 1 2 3 4 5 →