Design and FPGA Implementation of Matrix Multiplier Using DEMUX-RCA-Based Vedic Multiplier

Matrix multiplication is a common technique for increasing the computational speed of scientific and engineering tasks. The matrix multiplier is designed in this paper utilizing an optimized Vedic multiplier. Vedic mathematics, which is a collection of sutras for doing mathematical arithmetic simply and more speedily, is utilized to speed up multiplication. These sutras aid in the reduction of several processors performance metrics, such as power and delay. As a result, the current multiplier approaches are replaced with Urdhva Tiriyagbhyam, a Vedic Math multiplication methodology. We used 1:8 demultiplexer-based Full Adders (DFAs) to create the Vedic Multiplier to circumvent the power constraint. As a result, the overall power of matrix multiplication was improved across various bits. The Optimized Matrix multiplier is designed in Verilog HDL, and the Nexys DDR4 of the Artix-7 series is utilized as the target device for synthesis.