Functional Equivalence Verification Tools in High-Level Synthesis Flows

被引：21
|
作者：
Mathur, Anmol [1 ]
Clarke, Edmund [2 ]
Fujita, Masahiro [3 ]
Urard, Pascal [4 ]
机构：
[1] Calypto Design Syst, Santa Clara, CA 95054 USA
[2] Carnegie Mellon Univ, Pittsburgh, PA 15213 USA
[3] Univ Tokyo, Tokyo 1138654, Japan
[4] STMicroelectronics, Analog & Mixed Signals Grp, ST Technol R&D, Geneva, Switzerland
来源：
IEEE DESIGN & TEST OF COMPUTERS | 2009年 / 26卷 / 04期
关键词：
Algorithm design and analysis; Analytical models; Arrays; Computational modeling; Computer bugs; Correctness; Data mining; Design and test; Formal analysis; Functional equivalence; Logic gates; Sequential equivalence; System-level model;
D O I：
10.1109/MDT.2009.79
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Editor's note: High-level synthesis facilitates the use of formal verification methodologies that check the equivalence of the generated RTL model against the original source specification. The article provides an overview of sequential equivalence checking techniques, its challenges, and successes in real-world designs. -Andres Takach, Mentor Graphics © 2009 IEEE.
引用
收藏
页码：88 / 95
页数：8
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