Multi-DSP Implementation of a H. 264/SVC Decoder

被引：0
|
作者：
Pescador, F. [1 ,2 ,3 ]
Daian, A. [3 ]
Fernandez, I. [3 ]
Juarez, E. [1 ,2 ,3 ]
Garrido, M. [1 ,2 ,3 ]
机构：
[1] Univ Politecn Madrid, Elect & Microelect Design Grp GDEM, E-28040 Madrid, Spain
[2] Univ Politecn Madrid, Res Ctr Software Engn & Multimedia CITS, E-28040 Madrid, Spain
[3] Univ Politecn Madrid, E-28040 Madrid, Spain
来源：
2013 IEEE 17TH INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS (ISCE) | 2013年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, the implementation of a Multi-DSP based video decoder compliant with the H. 264/SVC standard (14496-10 Annex G) is presented. An optimized single DSP-based decoder implementation has been splitted in two processes: the frame decoding (entropy decoding and motion compensation) and the deblocking filter. A multi-DSP device has been used to parallelize the execution of the processes. The performance has been measured using H.264/SVC sequences with different configurations.
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页码：145 / +
页数：2
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