A new 6-bit flash A/D converter using novel two-step structure

In this study, we develop a new kind of 6-bit flash ADC with a new two-step structure to greatly reduce the chip size. The first coarse 4-bit uses an array of CMOS inverters rather than comparators for flash conversion. To detect various input signal levels, we adjust the ratio of channel length and width in the CMOS inverters to change the transition threshold. The result of coarse 4-bit is used to generate a reference level for fine 2-bit converting using full parallel structure. The advantages are that the ADC circuit can save reference resistors and reduce power dissipation. The new 6-bit ADC chip dissipates only 13mW using 0.35um process when it works at 100MHz.