A 6-bit 800-MS/s pipelined A/D converter with open-loop amplifiers

被引：25

作者：

Shen, Ding-Lan ^{[1
]}

Lee, Tai-Cheng

机构：

[1] Natl Taiwan Univ, Grad Inst elect Engn, Taipei 106, Taiwan

[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 106, Taiwan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2007年 / 42卷 / 02期

关键词：

analog-digital conversion; CMOS analog integrated circuits; gain control;

D O I：

10.1109/JSSC.2006.889380

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 6-bit 800-MS/s pipelined A/D converter (ADC) achieves SNDR and SFDR of 33.7 dB and 47.5 dB, respectively. Employing voltage-mode open-loop amplifiers in gain stages, global gain control techniques, and two-bank-interleaved architecture, the proposed pipelined A/D converter relaxes stringent design tradeoffs between speed and power. Fabricated in a 0.18-mu m CMOS technology, the ADC consumes 105 mW from a 1.8-V power supply while the active area is only 0.5 mm(2).

引用

页码：258 / 268

页数：11

共 50 条

[1] A 6-bit Pipelined Analog-to-Digital Converter with Current-Switching Open-Loop Residue Amplification
Hsieh, Fen-Chiu
Lee, Tai-Cheng
2008 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, 2008, : 61 - +
[2] A 9-bit 1.8-GS/s Pipelined ADC Using Linearized Open-Loop Amplifiers
Yu, Lilan
Miyahara, Masaya
Matsuzawa, Akira
2015 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2015, : 229 - 232
[3] A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers
Yu, Lilan
Miyahara, Masaya
Matsuzawa, Akira
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2016, 51 (10) : 2210 - 2221
[4] Power optimization for pipelined ADCs with open-loop residue amplifiers
Zanikopoulos, Athon
Harpe, Pieter
Hegt, Hans
van Roermund, Arthur
2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2006, : 132 - 135
[5] A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification
Murmann, B
Boser, BE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (12) : 2040 - 2050
[6] A 6-bit 500-Ms/s digital self-calibrated pipelined analog-to-digital converter
Chen, YH
Lee, TC
PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 2004, : 98 - 101
[7] A 6-Bit 800MS/s Flash ADC in 0.35μm CMOS
Ghasemzadeh, Mehdi
Soltani, Arefeh
Akbari, Amin
Hadidi, Khayrollah
2015 22ND INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS & SYSTEMS (MIXDES), 2015, : 234 - 238
[8] Design of a 11 bit 10Ms/s pipelined A/D converter
Peng, BL
Cheng, J
Chen, GC
2001 4TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, 2001, : 310 - 313
[9] Design of a 7-bit, 200MS/s, 2mW pipelined ADC with switched open-loop amplifiers in a 65nm CMOS technology
Wulff, Carsten
Ytterdal, Trond
2007 NORCHIP, 2007, : 73 - 76
[10] A 12-Bit, 300-MS/s Single-Channel Pipelined-SAR ADC With an Open-Loop MDAC
Wu, Chao
Yuan, Jie
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2019, 54 (05) : 1446 - 1454

← 1 2 3 4 5 →