High-speed network security - Architectures, algorithms, and implementations

被引:0
|
作者
Chao, H. Jonathan
Lau, Wing Cheong
Liu, Bin
Reiher, Peter
Talpade, Rajesh R.
Towlsey, D.
机构
[1] Polytech Univ, Dept Elect & Comp Engn, Brooklyn, NY 11201 USA
[2] Chinese Univ Hong Kong, Dept Informat Engn, Shatin, Hong Kong, Peoples R China
[3] Tsing Hua Univ, Dept Comp Sci & Technol, Beijing 100084, Peoples R China
[4] Univ Calif Los Angeles, Dept Comp Sci, Los Angeles, CA 90095 USA
[5] Telcordia Technol Inc, Piscataway, NJ 08854 USA
关键词
D O I
10.1109/JSAC.2006.877129
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:1777 / 1780
页数:4
相关论文
共 50 条
  • [21] On the dynamic performance of high-speed ADC architectures
    Gustavsson, M
    Tan, NX
    ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6, 1998, : 21 - 24
  • [22] High-Speed Architectures for Parallel BCH Decoders
    Wei Liu
    Zhao Lifeng
    FRONTIERS OF MANUFACTURING AND DESIGN SCIENCE IV, PTS 1-5, 2014, 496-500 : 2269 - +
  • [23] High-speed memory architectures for multimedia applications
    Oshima, Y
    Sheu, BJ
    Jen, SH
    IEEE CIRCUITS & DEVICES, 1997, 13 (01): : 8 - 13
  • [24] DFE architectures for high-speed backplane applications
    Li, M
    Wang, S
    Kwasniewski, T
    ELECTRONICS LETTERS, 2005, 41 (20) : 1115 - 1116
  • [25] A scalable family of high-speed switch architectures
    Al-Mouhamed, M
    ICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2003, : 32 - 35
  • [26] Device Architectures for High-speed SiGe HBTs
    Ruecker, H.
    Heinemann, B.
    2019 IEEE BICMOS AND COMPOUND SEMICONDUCTOR INTEGRATED CIRCUITS AND TECHNOLOGY SYMPOSIUM (BCICTS 2019), 2019,
  • [27] Architectures of high-speed wireless ATM networks
    Hac, A
    Hossain, A
    IEEE/AFCEA EUROCOMM 2000, CONFERENCE RECORD: INFORMATION SYSTEMS FOR ENHANCED PUBLIC SAFETY AND SECURITY, 2000, : 256 - 259
  • [28] High-speed VLSI architectures for the AES algorithm
    Zhang, XM
    Parhi, KK
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2004, 12 (09) : 957 - 967
  • [29] VLSI ARCHITECTURES FOR HIGH-SPEED RANGE ESTIMATION
    SASTRY, R
    RANGANATHAN, N
    JAIN, RC
    IEEE TRANSACTIONS ON PATTERN ANALYSIS AND MACHINE INTELLIGENCE, 1995, 17 (09) : 894 - 899
  • [30] VLSI architectures for high-speed MAP decoders
    Worm, A
    Lamm, H
    Wehn, N
    VLSI DESIGN 2001: FOURTEENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, 2001, : 446 - 453