Modified Lifting Scheme Algorithm for DWT with Optimized Latency & Throughput and FPGA Implementation for Low Power & Area

被引：0
|
作者：
Mohan, Murali S. [1 ]
Sathyanarayana, P. [2 ]
机构：
[1] SVCET, Dept ECE, Chittoor, AP, India
[2] SV Univ, Coll Engn, Dept ECE, Tirupati, Andhra Pradesh, India
来源：
2016 IEEE INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTER APPLICATIONS (ICACA) | 2016年
关键词：
Lifting Scheme; Pipelined Lifting DWT; FPGA; Throughput; Latency; ARCHITECTURE;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
The image processing applications require low power and high speed, the convolution based 1D-DWT is not desirable. In this proposed architecture the modified 5/3 lifting algorithm is realized on FPGA platform with optimizations. The latency and throughput is optimized with the modified algorithm. The architecture is modelled using HDL and implemented on FPGA. The proposal operates at 178MHz and realised for an area consumption of less than 1% with 24mW power consumption. The computed reports show performance improvement over existing techniques.
引用
收藏
页码：351 / 356
页数：6
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