A pulsed neural network with on-chip learning and its practical applications

被引：27

作者：

Zhuang, Hualiang ^{[1
]}

Low, Kay-Soon

Yau, Wei-Yun

机构：

[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore

[2] Inst Infocomm Res, Singapore, Singapore

来源：

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS | 2007年 / 54卷 / 01期

关键词：

field programmable gate array (FPGA); linear motors; pulsed neural network; radial basis function (RBF) neural network;

D O I：

10.1109/TIE.2006.888684

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a new model for the pulsed neural network. In this model, the information is coded in terms of firing times of pulses that are generated by the neuron. The pulses transmit through the network and excite the dynamics of the neuron. Their synchronism is utilized to design the architecture of the neural network such that it acts as a radial basis function (RBF) network. A new network-learning algorithm is also developed for this pulsed RBF network. The RBF neurons are generated based on the feature of the training data, and the synaptic delays can be adjusted to distribute these RBF neurons in the training data space. The pulse neural network has been implemented compactly with multiplierless approach for both the forward computation and learning algorithm with a field programmable gate array board. As an application demonstration, it is extended to a nonlinear look-up table and applied to estimate the friction occurs in a precision linear stage.

引用

页码：34 / 42

页数：9

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