The Effects of Dielectric Slots on Copper/Low-k Interconnects Reliability

被引：1

作者：

Heryanto, A. ^{[1
]}

Lim, Y. K. ^{[2
]}

Pey, K. L. ^{[1
]}

Liu, W. ^{[2
]}

Tan, J. B. ^{[2
]}

Sohn, D. K. ^{[2
]}

Hsia, L. C. ^{[2
]}

机构：

[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Nanyang Ave, Singapore 639798, Singapore

[2] Chartered Semicond Mfg Ltd, Singapore 738406, Singapore

来源：

PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2009年

关键词：

D O I：

10.1109/IITC.2009.5090349

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The effects of dielectric slots on Cu/Low-k interconnects reliability were studied. Dielectric slots were proven to be effective in suppressing stress-induced void failure but their impact on EM reliability was found to be minimal. Physical failure analysis and finite element simulations were used to explain the possible mechanisms associated to the different effects of dielectric slots on Cu/low-k reliability.

引用

页码：92 / +

页数：2

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