Packaging effects on reliability of Cu/Low-k interconnects

Chip-packaging interaction is becoming a critical reliability issue for Cu/low-k chips during assembly into a plastic flip-chip package. With the traditional TEOS interlevel dielectric being replaced by much weaker low-k dielectrics, packaging induced interfacial delamination in low-k interconnects has been widely observed, raising serious reliability concerns for Cu/low-k chips. In a flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/low-k interconnect structure inducing large local deformation to drive interfacial crack formation. In this paper, we summarize experimental and modeling results from studies performed in our laboratory to investigate the chip-package interaction and its impact on low-k interconnect reliability. We first review the experimental techniques for measuring thermal deformation in a flip-chip package and interfacial fracture energy for low-k interfaces. Then results from three-dimensional finite element analysis (FEA) based on a multilevel submodeling approach in combination with high-resolution moire interferometry to investigate the chip-package interaction for low-k interconnects are discussed. Packaging induced crack driving forces for relevant interfaces in Cu/low-k structures are deduced and compared with corresponding interfaces in Cu/TEOS and Al/TEOS, structures to assess the effect of ILD on packaging reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low-k structures.