InP DHBT technology and design for 40 Gbit/s full-rate-clock communication

被引：0

作者：

Godin, J ^{[1
]}

Riet, M ^{[1
]}

Blayac, S ^{[1
]}

Berdaguer, P ^{[1
]}

Dhalluin, V ^{[1
]}

Alexandre, F ^{[1
]}

Kahn, M ^{[1
]}

Pinquier, A ^{[1
]}

Kasbari, A ^{[1
]}

Moulu, J ^{[1
]}

Konczykowska, A ^{[1
]}

机构：

[1] ALCATEL R&I OPTO, F-91460 Marcoussis, France

来源：

GAAS IC SYMPOSIUM - 24TH ANNUAL, TECHNICAL DIGEST 2002 | 2002年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present our InP DHBT technology with improved performances, yield and uniformity; and some new designing tools, both of which have allowed to achieve 40+ Gbit/s full-rate-clock circuits, such as the D-Flip-Flop. These circuits have been characterized and packaged.

引用

页码：215 / 218

页数：4

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