40Gbit/s fully monolithic clock recovery IC using InAlAs/InGaAs/InP HEMTs

被引：8
|
作者：
Murata, K
Yamane, Y
机构：
[1] Nippon Telegraph & Tel Corp, Network Innovat Labs, Kanagawa 2390847, Japan
[2] Nippon Telegraph & Tel Corp, Photon Labs, Atsugi, Kanagawa 2430124, Japan
来源：
ELECTRONICS LETTERS | 2000年 / 36卷 / 19期
关键词：
D O I：
10.1049/el:20001163
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The authors describe a 40Gbit/s fully monolithic clock recovery integrated circuit (IC) fabricated using 0.1 mu m InAlAs/InGaAs/InP HEMTs. The IC utilises injection locking, and consists of a half bit delay, an exclusive OR gate and a T-type flip-flop. The IC extracts a half-rate clock signal from a 39.81312Gbit/s 2(31) - 1 pseudo-random bit sequence signal without any other external components.
引用
收藏
页码：1617 / 1618
页数：2
相关论文
共 50 条
  • [1] 40Gbit/s, fully-integrated 1:2 demultiplexer IC using InAlAs/InGaAs/InP HEMTs
    Otsuji, T
    Yoneyama, M
    Imai, Y
    Enoki, T
    Umeda, Y
    [J]. ELECTRONICS LETTERS, 1997, 33 (16) : 1409 - 1410
  • [2] 46Gbit/s multiplexer and 40Gbit/s demultiplexer IC modules using InAlAs/InGaAs/InP HEMTs
    Otsuji, T
    Yoneyama, M
    Imai, Y
    Yamaguchi, S
    Enoki, T
    Umeda, Y
    Sano, E
    [J]. ELECTRONICS LETTERS, 1996, 32 (07) : 685 - 686
  • [3] 64Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTs
    Otsuji, T
    Yoneyama, M
    Imai, Y
    Enoki, T
    Umeda, Y
    [J]. ELECTRONICS LETTERS, 1997, 33 (17) : 1488 - 1489
  • [4] 80Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTs
    Otsuji, T
    Murata, K
    Enoki, T
    Umeda, Y
    [J]. ELECTRONICS LETTERS, 1998, 34 (01) : 113 - 114
  • [5] An 80-Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTs
    Otsuji, T
    Murata, K
    Enoki, T
    Umeda, Y
    [J]. GAAS IC SYMPOSIUM - 19TH ANNUAL, TECHNICAL DIGEST 1997, 1997, : 183 - 186
  • [6] 45Gbit/s decision IC module using InAlAs/InGaAs/InP HEMTs
    Murata, K
    Otsuji, T
    Yamane, Y
    [J]. ELECTRONICS LETTERS, 1999, 35 (16) : 1379 - 1380
  • [7] 50-Gbit/s demultiplexer IC module using InAlAs/InGaAs/InP HEMTs
    Sano, K
    Murata, K
    Yamane, Y
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 2000, E83C (11) : 1786 - 1788
  • [8] 40Gbit/s optical repeater circuit using InAlAs/InGaAs HEMT digital IC modules
    Yoneyama, M
    Sano, A
    Kataoka, T
    Hirano, A
    Otsuji, T
    Sato, K
    Miyazawa, H
    Hagimoto, K
    [J]. ELECTRONICS LETTERS, 1997, 33 (23) : 1977 - 1978
  • [9] 70-Gbit/s multiplexer and 50-Gbit/s decision IC modules using InAlAs/InGaAs/InP HEMTs
    Murata, Koichi
    Otsuji, Taiichi
    Sano, Eiichi
    Kimura, Shunji
    Yamane, Yasuro
    [J]. 2000, IEICE of Japan, Tokyo, Japan (E83-C)
  • [10] 70-Gbit/s multiplexer and 50-Gbit/s decision IC modules using InAlAs/InGaAs/InP HEMTs
    Murata, K
    Otsuji, T
    Sano, E
    Kimura, S
    Yamane, Y
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 2000, E83C (07) : 1166 - 1169
12345