43 Gb/s decision circuits in InP DHBT technology

被引：4
|
作者：
Krishnamurthy, K [1 ]
Chow, J
Mensa, D
Pullela, R
机构：
[1] Gtran Inc, Newbury Pk, CA 91320 USA
[2] Northrop Grumman, Redondo Beach, CA 90278 USA
[3] Skyworks Inc, Irvine, CA 92612 USA
来源：
IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS | 2004年 / 14卷 / 01期
关键词：
flip-flops; frequency divider; HBT; high-speed integrated circuits; InP; retimer;
D O I：
10.1109/LMWC.2003.821504
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Packaged master-slave D-flip-flops designed in InP DHBT technology with 150 GHz f(t) and 180 GHz f(max) are presented. Measurement results using a 43.2 Gb/s nonreturn to zero (NRZ), pseudo random binary sequence (PRBS) data (generated from 4 channels of 10.8 Gb/s, 2(31) - 1, PRBS data) and a 43.2 GHz clock, show a clock phase margin of 190degrees. 2:1 Static frequency dividers designed using the D-flip-flops have been tested up to 50 GHz and show normal operation. These circuits are key building blocks in numerous front-end circuits used for 40 Gb/s optical communication systems.
引用
收藏
页码：28 / 30
页数：3
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