A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory

被引：0

作者：

Yoshida, E ^{[1
]}

Tanaka, T ^{[1
]}

机构：

[1] Fujitsu Labs Ltd, Akiruno 1970833, Japan

来源：

2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST | 2003年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A capacitorless IT-DRAM cell using gate-induced drain leakage (GIDL) current for write operation was demonstrated for the first time. Compared with the conventional write operation with impact ionization current, write operation with GIDL current provides low-power and high-speed operation. The capacitorless IT-DRAM is the most promising technology for high performance embedded DRAM LSI.

引用

页码：913 / 916

页数：4

共 22 条

[1] A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory
Yoshida, E
Tanaka, T
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (04) : 692 - 697
[2] A Capacitor-less 1T-DRAM Cell with Vertical Surrounding Gates Using Gate-Induced Drain-Leakage (GIDL) Current
Chung, Han Ki
Jeong, Hoon
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[3] FDSOI Floating Body Cell eDRAM Using Gate-Induced Drain-Leakage (GIDL) Write Current for High Speed and Low Power Applications
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[4] Revisiting Lateral-BTBT Gate-Induced Drain Leakage in Nanowire FETs for 1T-DRAM
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[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2024, 71 (04) : 2714 - 2720
[5] A NOVEL FINFET-BASED 1T-DRAM WITH EXTENDED BODY USING GATE-INDUCED DRAIN LEAKAGE MECHANISM
Huang, Zih-Hao
Lin, Jyi-Tsong
Lin, Po-Hsieh
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[J]. 2014 12TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2014,
[6] A High Speed Low Power Capacitorless SOI-DRAM Cell Using Impact Ionization and GIDL Effect
Hou, Jianing
Shao, Zhibiao
Miao, Xin
[J]. 2009 IEEE INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC 2009), 2009, : 517 - 520
[7] Competitive 1T-DRAM in 28 nm FDSOI Technology for Low-Power Embedded Memory
El Dirani, H.
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[J]. 2016 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2016,
[8] Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)
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[9] Using GIDL mechanism for Low-Power Consumption and Data Retention Time Improvement in a Double-Gate Nanowire TFT 1T-DRAM with Fin-Gate and Pillar-Body Structure
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Lin, Jyi-Tsong
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[J]. PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2015,
[10] Design of High-Speed, Low-Power Sensing Circuits for Nano-Scale Embedded Memory
Lee, Sangheon
Park, Gwanwoo
Jeong, Hanwool
[J]. SENSORS, 2024, 24 (01)

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