A parallel approach solving the test generation problem for synchronous sequential circuits

Automatic test pattern generation yielding high fault coverage for CMOS circuits has received a wide attention in industry and academic for a long time. Since ATPG is an NP complete problem with complexity exponential to the number of circuit elements, the parallelization of ATPG is an attractive topic of research. In this paper we describe a parallel sequential ATPG approach which is either running on a standard network of UNIX workstations and also, without any changing of the source code, on one of the most powerful high performance parallel computers, the IBM SP2. The test pattern generation is performed in three phases, two for easy-to-detect faults, using fault parallelism with an adapting limit for the number of backtracks and a third phase for hard-ro-detect faults, using search tree parallelism. The main advantage over existing approaches is a dynamic solution for partitioning the fault list and the search tree resulting in a very small overhead for communication without the need of any broadcasts and an optimal load balancing without idle times for the test pattern generators.