On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits

被引:0
|
作者
Pomeranz, Irith [1 ]
Reddy, Sudhakar M. [2 ]
机构
[1] Purdue Univ, Sch ECE, W Lafayette, IN 47907 USA
[2] Univ Iowa, ECE Dept, Iowa City, IA 52242 USA
关键词
diagnostic test generation; functional test generation; state transition faults; synchronous sequential circuits;
D O I
10.1016/j.entcs.2006.12.031
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
We study the relationship between diagnostic test generation for a gate-level fault model, which is used for generating diagnostic test sets for manufacturing defects, and functional test generation for a high-level fault model. In general, a functional fault may partially represent some of the effects of one gate-level fault but not another. Generating a test sequence for the functional fault is then likely to detect one gate-level fault but not the other, thus distinguishing the two faults. This relationship points to the ability to use a functional test generation procedure (that targets functional fault detection) as a way of generating diagnostic test sequences for gate-level faults. We use this observation in two ways. The more direct way is to define functional faults that correspond to the differences between pairs of gate-level faults. The second way is to use functional test sequences as diagnostic test sequences without explicitly considering gate-level faults. We support the use of the resulting procedures with experimental results.
引用
收藏
页码:83 / 93
页数:11
相关论文
共 50 条
  • [1] Functional test generation for synchronous sequential circuits
    Srinivas, MK
    Jacob, J
    Agrawal, VD
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1996, 15 (07) : 831 - 843
  • [2] A diagnostic test generation procedure for synchronous sequential circuits based on test elimination
    Pomeranz, I
    Reddy, SM
    [J]. INTERNATIONAL TEST CONFERENCE 1998, PROCEEDINGS, 1998, : 1074 - 1083
  • [3] Diagnostic test generation for sequential circuits
    Yu, XM
    Wu, J
    Rudnick, EM
    [J]. INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS, 2000, : 225 - 234
  • [4] Diagnostic test generation procedure based on test elimination by vector omission for synchronous sequential circuits
    Pomeranz, I
    Reddy, SM
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2000, 19 (05) : 589 - 600
  • [5] Diagnostic test pattern generation for sequential circuits
    Hartanto, I
    Boppana, V
    Patel, JH
    Fuchs, WK
    [J]. 15TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1997, : 196 - 202
  • [6] Modified test generation methods for synchronous sequential circuits
    Kemamalini, A.
    Seshasayanan, R.
    [J]. 2015 INTERNATIONAL CONFERENCE ON INNOVATIONS IN INFORMATION, EMBEDDED AND COMMUNICATION SYSTEMS (ICIIECS), 2015,
  • [7] Templates: A test generation procedure for synchronous sequential circuits
    Pomeranz, I
    Reddy, SM
    [J]. SIXTH ASIAN TEST SYMPOSIUM (ATS'97), PROCEEDINGS, 1997, : 74 - 79
  • [8] MIX: A test generation system for synchronous sequential circuits
    Lin, XJ
    Pomeranz, I
    Reddy, SM
    [J]. ELEVENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 456 - 463
  • [9] Built-in test generation for synchronous sequential circuits
    Pomeranz, I
    Reddy, SM
    [J]. 1997 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS, 1997, : 421 - 426
  • [10] FsmTest: Functional test generation for sequential circuits
    Buonanno, G
    Fummi, F
    Sciuto, D
    Lombardi, F
    [J]. INTEGRATION-THE VLSI JOURNAL, 1996, 20 (03) : 303 - 325