A 32-bit carry lookahead adder using dual-path all-N logic

被引：18

作者：

Yang, G ^{[1
]}

Jung, SO

Baek, KH

Kim, SH

Kim, S

Kang, SM

机构：

[1] Nvidia Corp, Santa Clara, CA 95050 USA

[2] Qualcomm Inc, San Diego, CA 92121 USA

[3] Rockwell Sci, Thousand Oaks, CA 91360 USA

[4] Korea Univ, Seoul 136701, South Korea

[5] Univ Calif Santa Cruz, Santa Cruz, CA 95064 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2005年 / 13卷 / 08期

关键词：

CMOs; dynamic-logic circuit; high performance; low-power design;

D O I：

10.1109/TVLSI.2005.853605

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We have developed dual path all-N logic (DPANL) and applied it to 32-bit adder design for higher performance. The speed is significantly enhanced due to reduced capacitance at each evaluation node of dynamic circuits. The power saving is achieved due to reduced adder cell size and minimal race problem. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35-mu m 1P4M CMOS technology and is 32.4% faster than the adder using all-N transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35-mu m CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.

引用

页码：992 / 996

页数：5

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