A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme

被引：0

作者：

Kim, YJ ^{[1
]}

Sung, KH ^{[1
]}

Kim, LS ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Dept EECS, Yusong Gu, Taejon 305701, South Korea

来源：

2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, PROCEEDINGS | 2002年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Using carry-select adder scheme, an adder with small number of stages can operate as fast as an adder with large number of stages. In this paper, a 4-block 5-stage 32-bit pipelined carry-select adder is designed and implemented. The proposed adder operates as fast as a conventional 16-stage 32-bit pipelined ripple-carry adder while number of registers required is nearly same as a conventional 4-stage pipelined adder. This adder is operated at 1.67 GHz clock frequency in a standard 0.25um CMOS technology with 2.5 V supply voltage.

引用

页码：461 / 464

页数：4

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