A Study of an Infrastructure for Research and Development of Many-Core Processors

被引：2
|
作者：
Uehara, Koh [1 ]
Sato, Shimpei [1 ]
Miyoshi, Takefumi [1 ]
Kise, Kenji [1 ]
机构：
[1] Tokyo Inst Technol, Grad Sch Informat Sci & Engn, Tokyo, Japan
来源：
2009 INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED COMPUTING, APPLICATIONS AND TECHNOLOGIES (PDCAT 2009) | 2009年
关键词：
D O I：
10.1109/PDCAT.2009.77
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Many-core processors which have thousands of cores on a chip will be realized. We developed an infrastructure which accelerates the research and development of such many-core processors. This paper describes three main elements provided by our infrastructure. The first element is the definition of simple many-core processor architecture called M-Core. The second is SimMc, a software simulator of M-Core. The third is the software library MClib which helps the development of application programs for M-Core. The simulation speed of SimMc and the parallelization efficiency of M-Core are evaluated using some benchmark programs. We show that our infrastructure accelerates the research and development of many-core processors.
引用
收藏
页码：414 / 419
页数：6
相关论文
共 50 条
  • [31] Online Periodic Test Mechanism for Homogeneous Many-core Processors
    Kamran, Arezoo
    Navabi, Zainalabedin
    2013 IFIP/IEEE 21ST INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC), 2013, : 256 - 259
  • [32] Tailoring Genetic Algorithm for Resource Scheduling in Many-Core Processors
    Hu, Xiande
    Li, Jingming
    Cheng, Jiaxing
    PROCEEDINGS OF THE 2015 2ND INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER ENGINEERING AND ELECTRONICS (ICECEE 2015), 2015, 24 : 465 - 471
  • [33] Approximate Set Similarity Join Using Many-Core Processors
    Sugano, Kenta
    Amagasa, Toshiyuki
    Kitagawa, Hiroyuki
    DATABASE AND EXPERT SYSTEMS APPLICATIONS (DEXA 2018), PT II, 2018, 11030 : 214 - 222
  • [34] Reducing the burden of parallel loop schedulers for many-core processors
    Arif, Mahwish
    Vandierendonck, Hans
    CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 2021, 33 (13):
  • [35] Algorithmic Patterns for H-Matrices on Many-Core Processors
    Zaspel, Peter
    JOURNAL OF SCIENTIFIC COMPUTING, 2019, 78 (02) : 1174 - 1206
  • [36] Method of independent debug system design for many-core processors
    Zhang, Ming
    Shi, Wei
    Guo, Yu-Feng
    Zhang, Min-Xuan
    Hunan Daxue Xuebao/Journal of Hunan University Natural Sciences, 2015, 42 (04): : 93 - 99
  • [37] All-pairs computations on many-core graphics processors
    Sarje, Abhinav
    Aluru, Srinivas
    PARALLEL COMPUTING, 2013, 39 (02) : 79 - 93
  • [38] Thermal Investigation Into Power Multiplexing for Homogeneous Many-Core Processors
    Gupta, Man Prakash
    Cho, Minki
    Mukhopadhyay, Saibal
    Kumar, Satish
    JOURNAL OF HEAT TRANSFER-TRANSACTIONS OF THE ASME, 2012, 134 (06):
  • [39] Greening of Many-Core Processors in Network-Optimized Computing
    Inoue, Hiroaki
    Ishizaka, Kazuhisa
    Sakai, Junji
    2011 IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE (GLOBECOM 2011), 2011,
  • [40] Hardware Acceleration of Online Error Detection in Many-Core Processors
    Kamran, Arezoo
    Navabi, Zainalabedin
    CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE, 2015, 38 (02): : 143 - 153
12345