A new optimization cost model for VLSI standard cell placement

被引：0
|
作者：
Cheung, PYS
Yeung, CSK
Tse, SK
Yuen, CK
Ko, WL
机构：
来源：
ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE | 1997年
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D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
In this paper, we propose a new optimization cost model for VLSI placement. It distinguishes itself from the traditional wire-length cost model[2][3][6] by having direct impact on the quality of the detailed routing phase, We also extend the well-known simulated annealing standard cell placement algorithm by applying our new cost model. Experimental results shows that we got 13% layout area reduction compared to traditional wire length model, 11% reduction to commercial tool.
引用
收藏
页码：1708 / 1711
页数：4
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