A multiplexer based test method for self-timed circuits

被引:0
|
作者
te Beest, F [1 ]
Peeters, A [1 ]
机构
[1] Philips Technol Incubator, Handshake Solut, Eindhoven, Netherlands
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A new test method for self-timed circuits is presented that only uses multiplexers to make the majority of combinational feedback loops testable. Combinational feedback loops are problematic for testing, since they introduce sequential behavior in a circuit. Traditionally feedback loops are broken with scan latches or even scan flip-flops, which causes not only a large area overhead, but also have a large impact on performance. The method we present significantly reduces the cost of testing a self-timed circuit, while it retains all the benefits of traditional scan test methods. Most importantly, the method remains fully compatible with standard combinational test pattern generation tools and provides up to 100% stuck-at-fault coverage. With the presented test method it becomes cost effective to use scan test for a self-timed circuit without the need to add new specialized cells to a standard cell library.
引用
下载
收藏
页码:166 / 175
页数:10
相关论文
共 50 条
  • [21] Optimization of NULL convention self-timed circuits
    Smith, SC
    DeMara, RF
    Yuan, JS
    Ferguson, D
    Lamb, D
    INTEGRATION-THE VLSI JOURNAL, 2004, 37 (03) : 135 - 165
  • [22] Avoiding hazards in self-timed digital circuits
    ATR, Australian Telecommunication Research, 29 (01):
  • [23] Self-Timed Circuits FPGA Implementation Flow
    Fiorentino, Mickael
    Al-Terkawi, Omar
    Savaria, Yvon
    Thibeault, Claude
    2015 IEEE 13TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 2015,
  • [24] IMPLEMENTING SEQUENTIAL-MACHINES AS SELF-TIMED CIRCUITS
    DAVID, I
    GINOSAR, R
    YOELI, M
    IEEE TRANSACTIONS ON COMPUTERS, 1992, 41 (01) : 12 - 17
  • [25] C-elements for Hardened Self-timed Circuits
    Ouchet, Florent
    Morin-Allory, Katell
    Fesquet, Laurent
    INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION, AND SIMULATION, 2011, 6951 : 247 - 256
  • [26] Power, Delay and Area Efficient Self-Timed Multiplexer and Demultiplexer Designs
    Balasubramanian, P.
    Edwards, D. A.
    DTIS: 2009 4TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA, PROCEEDINGS, 2009, : 173 - 178
  • [27] Self-timed, minimum latency circuits for the internet of things
    Wheeldon, Adrian
    Morris, Jordan
    Sokolov, Danil
    Yakovlev, Alex
    INTEGRATION-THE VLSI JOURNAL, 2019, 69 : 138 - 146
  • [28] On Self-Timed Circuits in Real-Time Systems
    Ferringer, Markus
    INTERNATIONAL JOURNAL OF RECONFIGURABLE COMPUTING, 2011, 2011
  • [29] Analog Self-Timed Programming Circuits for Aging Memristors
    Irmanova, Aidana
    Maan, Akshay
    James, Alex
    Chua, Leon
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68 (04) : 1133 - 1137
  • [30] AN EFFICIENT IMPLEMENTATION OF BOOLEAN FUNCTIONS AS SELF-TIMED CIRCUITS
    DAVID, I
    GINOSAR, R
    YOELI, M
    IEEE TRANSACTIONS ON COMPUTERS, 1992, 41 (01) : 2 - 11