A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations

A novel high speed 4-2 compressor using static and pass-transistor logic, has been designed in a 0.35 mu m CMOS technology. In order to reduce gate level delay and increase the speed, some changes are performed in truth table of conventional 4-2 compressor which leaded to the simplification of logic function for all parameters. Therefore, power dissipation is decreased. In addition, because of similar paths from all inputs to the outputs, the delays are the same. So there will be no need for extra buffers in low latency paths to equalize the delays.