A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations

被引：0

作者：

Fathi, Amir ^{[1
]}

Azizian, Sarkis ^{[1
]}

Hadidi, Khayrollah ^{[1
]}

Khoei, Abdollah ^{[1
]}

机构：

[1] Urmia Univ, Microelect Res Lab, Orumiyeh 57159, Iran

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2012年 / E95C卷 / 04期

关键词：

compressor; low latency; pass-transistor logic;

D O I：

10.1587/transele.E95.C.710

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel high speed 4-2 compressor using static and pass-transistor logic, has been designed in a 0.35 mu m CMOS technology. In order to reduce gate level delay and increase the speed, some changes are performed in truth table of conventional 4-2 compressor which leaded to the simplification of logic function for all parameters. Therefore, power dissipation is decreased. In addition, because of similar paths from all inputs to the outputs, the delays are the same. So there will be no need for extra buffers in low latency paths to equalize the delays.

引用

页码：710 / 712

页数：3

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