共 50 条
- [41] A high performance JPEG2000 architecture 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, PROCEEDINGS, 2002, : 765 - 768
- [42] Novel architecture of EBC for JPEG2000 19TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2005, : 530 - 533
- [44] A DUAL SYMBOL ARITHMETIC CODER ARCHITECTURE WITH REDUCED MEMORY FOR JPEG2000 2010 IEEE INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, 2010, : 513 - 516
- [45] JPEG2000 encoding with perceptual distortion control 2003 INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, VOL 1, PROCEEDINGS, 2003, : 637 - 640
- [46] Efficient JPEG2000 EBCOT Context Modeling for Massively Parallel Architectures 2011 DATA COMPRESSION CONFERENCE (DCC), 2011, : 423 - 432
- [47] An Efficient, High Speed Architecture for JPEG2000 MQ-Coder 2014 FIRST INTERNATIONAL IMAGE PROCESSING, APPLICATIONS AND SYSTEMS CONFERENCE (IPAS), 2014,
- [49] Efficient VLSI architecture for buffer used in EBCOT of JPEG2000 encoder 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 4361 - 4364
- [50] An efficient accelerating architecture for tier-1 coding in JPEG2000 2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS, 2004, : 1653 - 1656