A 5mW 19-43 GHz broadband CMOS I/Q frequency divider

被引：0
|
作者：
Sharaf, Khaled M. [1 ]
机构：
[1] Ain Shams Univ, Fac Engn, Integrated Circuits Lab, Cairo, Egypt
来源：
PROCEEDINGS OF THE 25TH NATIONAL RADIO SCIENCE CONFERENCE: NRSC 2008 | 2008年
关键词：
D O I：
暂无
中图分类号：
TN [电子技术、通信技术];
学科分类号：
0809 ;
摘要：
A comparison of three designs of high-frequency broadband frequency dividers is presented. The designs are optimized for high operating frequencies. Two recently published dynamic-loading frequency divider designs are optimized for their highest attainable speed. The third proposed frequency divider features it modified dynamic-loading master-slave D-latches with on-chip spiral inductors at its differential clock inputs. The proposed frequency divider is designed in TSMC 0.13-mu m CMOS process and can operate in the 19-43 GHz range and dissipates 5 mW from a supply voltage of 1.5V.
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收藏
页码：U765 / U772
页数：8
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