Design of 10 GHz, 2.6 mW frequency divider in 0.25 μm CMOS

被引：0

作者：

He, CM ^{[1
]}

Sun, YH ^{[1
]}

机构：

[1] Tsing Hua Univ, Inst Microelect, Beijing 100084, Peoples R China

来源：

SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1 AND 2, PROCEEDINGS | 2001年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes the design of high speed, low power-dissipation frequency divider. The circuit has wide applications in high-speed communication systems, especially in clock recovery and frequency synthesis. Since frequency divider is one of the key parts in the frequency synthesis, divider's speed limits the precision and the frequency of the frequency synthesis. In the paper, a frequency divider configured as master-slave flip-flop based on RAM cell is presented. Using TSMC 0.25um CMOS SPICE parameters, the divider circuit is simulated with HSPICE and get such results: while operating at 10 GHz with the 2V supply voltage, it dissipates only 2.6mW.

引用

页码：1136 / 1138

页数：3

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