A novel 18 GHz 1.3 mW CMOS frequency divider with high input sensitivity

被引：0

作者：

Fard, A ^{[1
]}

Åberg, D ^{[1
]}

机构：

[1] Malardalen Univ, Dept Comp Sci & Elect, SE-72123 Vasteras, Sweden

来源：

ISSCS 2005: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS | 2005年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel CMOS, high speed divide-by-two circuit with very low power consumption Is proposed in this paper. The circuit features very low input capacitance and a wide locking range of 1.5-18 GHz with a power consumption of less than 13 mW at 1.8 V. The input sensitivity of the stage is improved significantly when compared to conventional dynamic loaded high frequency dividers. The concept and design issue of the circuit is presented together with a performance comparison to existing topologies. The idea is demonstrated, and verified in a standard 0.18 mu m CMOS process through realistic simulations originating from a complete layout using moderately extracted parasitics.

引用

页码：409 / 412

页数：4

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