A 5.3-GHz programmable divider for HiPerLAN in 0.25-μm CMOS

A 5.3-GHz low-voltage CMOS frequency divider whose modulus can be varied from 220 to 224 is presented. Programmability is achieved by switching between different output phases of a D-flip-flop (DFF), An improved glitch-free phase switching architecture through the use of retimed multiplexer control signals is introduced, A high-speed low-voltage DFF circuit is given. The programmable divider fabricated in 0.25-mu m technology occupies 0.09 mm(2); it consumes 17.4 mA at 1.8 V and 26.8 mA at 2.2 V, Operation of 5.5 GHz with 300-mV(pk) single-ended input is achieved with a 2.2-V supply. The residual phase noise at the output is -131 dBc/Hz at an offset of 1 kHz from the carrier while operating from a 5.5-GHz input.