A 43-GHz static frequency divider in 0.13μm standard CMOS

被引：0
|
作者：
Liang, Bangli [1 ]
Chen, Dianyong [1 ]
Wang, Bo [1 ]
Cheng, Dezhong [1 ]
Kwasniewski, Tad [1 ]
机构：
[1] Carleton Univ, Dept Elect, Ottawa, ON K1S 5B6, Canada
来源：
2008 CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, VOLS 1-4 | 2008年
关键词：
CML; frequency divider; SP; SR;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, a low supply static 2:1 frequency divider based on 0.13 mu m CMOS is presented. It is designed for 40-Gb/s optical communication systems. Current-mode logic (CML) is adopted because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. This frequency divider is designed with output buffer to drive the external 50 Omega loads. On-chip shunt peaking (SP) inductors and split-resistor (SR) loads are used to boost the bandwidth. The frequency divider uses a single 1.2-V supply voltage and consumes a total current of 32mA. And the chip area is only 0.63mm(2) with bonding pads.
引用
收藏
页码：107 / 110
页数：4
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