On-chip bist-based diagnosis of embedded programmable logic cores in system-on-chip devices

被引:0
|
作者
Stroud, C [1 ]
Garimella, S [1 ]
Sunwoo, J [1 ]
机构
[1] Auburn Univ, Dept Elect & Comp Engn, Auburn, AL 36849 USA
关键词
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
On-chip Built-In Self-Test (BIST) based diagnosis of the embedded Field Programmable Gate Array (FPGA) core in a generic System-on-Chip (SoC) is presented. In this approach, the embedded processor core in the SoC is used for reconfiguration of the FPGA core for BIST, initiating the BIST sequence, retrieving the BIST results, and for performing diagnosis of faulty programmable logic blocks, memory cores, programmable interconnect resources within the FPGA core based on failing BIST results. These BIST and BIST-based diagnostic procedures have been implemented and verified on a commercial SoC with fault injection emulation. Diagnostic resolution is achieved to the faulty logic or memory block and can be used for on-chip reconfiguration to bypass faulty resources for fault-tolerant applications.
引用
收藏
页码:308 / 313
页数:6
相关论文
共 50 条
  • [41] Using on-chip configurable logic to reduce embedded system software energy
    Stitt, G
    Grattan, B
    Villarreal, J
    Vahid, F
    10TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS, 2002, : 143 - 151
  • [42] An embedded DRAM macro architecture for system-on-chip
    Sunaga, T
    Hosokawa, K
    Watanabe, S
    Mori, M
    CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE, 2001, 26 (3-4): : 131 - 134
  • [43] Development of multiprocessor system-on-chip based on soft processor cores schoolMIPS
    Ryazanova, A. E.
    Amerikanov, A. A.
    Lezhnev, E. V.
    INTERNATIONAL CONFERENCE ON COMPUTER SIMULATION IN PHYSICS AND BEYOND, 2019, 1163
  • [44] An embedded DRAM macro architecture for system-on-chip
    Sunaga, Toshio
    Hosokawa, Kohji
    Watanabe, Shinpei
    Mori, Masaya
    Canadian Journal of Electrical and Computer Engineering, 2001, 26 (3-4) : 131 - 134
  • [45] Multiprocessor architectures for embedded system-on-chip applications
    Ravikumar, CP
    17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA, 2004, : 512 - 519
  • [46] An embedded tester core for system-on-chip architectures
    Rashidzadeh, R
    Ahmadi, M
    Miller, WC
    4TH IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, 2004, : 105 - 108
  • [47] Legal protection on ip cores for system-on-chip designs
    Kinoshita T.
    IEEJ Transactions on Electronics, Information and Systems, 2011, 131 (02) : 265 - 270
  • [48] Programmable parallel coprocessor architectures for reconfigurable system-on-chip
    Williams, J
    Bergmann, N
    2004 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, PROCEEDINGS, 2004, : 193 - 200
  • [49] Multifunctional Programmable System-on-Chip for Heterogeneous Signals Processing
    Krylov, S. M.
    Orlov, S. P.
    Saraev, M., V
    2017 INTERNATIONAL CONFERENCE ON INDUSTRIAL ENGINEERING, APPLICATIONS AND MANUFACTURING (ICIEAM), 2017,
  • [50] Scheduling of cores for power constrained system-on-chip testing
    Chakraborty, Rupsa
    Chowdhury, Dipanwita Roy
    ADCOM 2007: PROCEEDINGS OF THE 15TH INTERNATIONAL CONFERENCE ON ADVANCED COMPUTING AND COMMUNICATIONS, 2007, : 9 - +