Scheduling of cores for power constrained system-on-chip testing

A system-on-chip (SOC) may contain numerous cores. If each core has its own distinct set of tests then in order to reduce the total testing time some of these cores may be tested in parallel. The order of such testing is determined by a schedule. An efficient scheduling algorithm can bring about a considerable reduction in the total test time of chips for large scale testing. This paper proposes a heuristic for scheduling large number of cores in SOC testing. The scheduling algorithm is very fast and hence can tackle the problem of scheduling in SOCs having numerous cores. It works with constrained power and limited SOC TAM width and aims to reduce total test time. The elegance of the heuristic is supported by the extensive experimental results.