A Transaction-Level Framework for Design-Space Exploration of Hardware-Enhanced Operating Systems

被引：0

作者：

Gregorek, Daniel ^{[1
]}

Garcia-Ortiz, Alberto ^{[1
]}

机构：

[1] Univ Bremen, ITEM, Integrated Digital Syst Grp, D-28359 Bremen, Germany

来源：

2014 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP (SOC) | 2014年

关键词：

transaction-level; hardware operating system; trace-driven simulation; design space exploration;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

The increasing number of processing elements on embedded many-cores gives novel challenges for the chip design. Dedicated hardware has become an important feature to support the applied operating system and to improve the overall system efficiency. Since evaluation of novel architectures requires time expensive simulations or prototyping, transaction-level analysis gives an appropriate tool for early design stage evaluation. This work proposes a transaction-level framework for simulating hardware-enhanced many-core operating systems. The framework allows the design space exploration of the hardware and software architecture and uses a trace-based task description language including a customized interface for system calls.

引用

页数：4

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