A balanced clock network design algorithm for clock delay, skew, and power optimization with slew rate constraint

被引：0
|
作者：
Sulaiman, MS [1 ]
机构：
[1] Multimedia Univ, Fac Engn, Cyberjaya 63100, Selangor, Malaysia
来源：
2002 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS | 2002年
关键词：
high performance; IC design; low power design;
D O I：
10.1109/SMELEC.2002.1217776
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A heuristic algorithm for optimized clock network design is presented. The algorithms for optimization of clock skew, delay, and power considering slew rate constraint for a balanced IC clock tree are implemented using a modified method of cautious approach. Algorithms developed are verified with the model of a real chip, i.e. post layout model of an FPGA chip. HSpice simulations at 115degreesC, with CMOS 0.35 mum models and parameters show. a 60% reduction in the clock slew rate and a 23% improvement in the power dissipation when compared to. the results of the initial, unoptimized chip.
引用
收藏
页码：62 / 66
页数：5
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