A balanced clock network design algorithm for clock delay, skew, and power optimization with slew rate constraint

被引：0
|
作者：
Sulaiman, MS [1 ]
机构：
[1] Multimedia Univ, Fac Engn, Cyberjaya 63100, Selangor, Malaysia
来源：
2002 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS | 2002年
关键词：
high performance; IC design; low power design;
D O I：
10.1109/SMELEC.2002.1217776
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A heuristic algorithm for optimized clock network design is presented. The algorithms for optimization of clock skew, delay, and power considering slew rate constraint for a balanced IC clock tree are implemented using a modified method of cautious approach. Algorithms developed are verified with the model of a real chip, i.e. post layout model of an FPGA chip. HSpice simulations at 115degreesC, with CMOS 0.35 mum models and parameters show. a 60% reduction in the clock slew rate and a 23% improvement in the power dissipation when compared to. the results of the initial, unoptimized chip.
引用
收藏
页码：62 / 66
页数：5
相关论文
共 50 条
  • [41] Power Clock Generator design Using Delay Locked Loop For Adiabatic Logic
    Pittala, Suresh Kumar
    Rani, A. Jhansi
    PROCEEDINGS OF THE 2017 IEEE SECOND INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER AND COMMUNICATION TECHNOLOGIES (ICECCT), 2017,
  • [42] A high-level optimization scheme for low power clock design
    Kang, CJ
    Chen, CH
    CCCT 2003, VOL6, PROCEEDINGS: COMPUTER, COMMUNICATION AND CONTROL TECHNOLOGIES: III, 2003, : 221 - 224
  • [43] A high-level optimization scheme for low power clock design
    Kang, CJ
    Chen, CH
    Adel-Raheem, E
    PROCEEDINGS OF THE 46TH IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS & SYSTEMS, VOLS 1-3, 2003, : 1492 - 1495
  • [44] ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design
    Teng, Ying
    Taskin, Baris
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (11) : 2519 - 2530
  • [45] An Efficient Algorithm of Adjustable Delay Buffer Insertion for Clock Skew Minimization in Multiple Dynamic Supply Voltage Designs
    Lin, Kuan-Yu
    Lin, Hong-Ting
    Ho, Tsung-Yi
    2011 16TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2011,
  • [46] A fuzzy-based algorithm to remove clock skew and reset from one-way delay measurement
    Lin, Y
    Kuo, GS
    Wang, HB
    Cheng, SD
    Zou, SH
    GLOBECOM '04: IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE, VOLS 1-6, 2004, : 1425 - 1430
  • [47] Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint
    Tanaka, Mikiko Sode
    Togawa, Nozomu
    Yanagisawa, Masao
    Goto, Satoshi
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2011, E94A (04) : 1082 - 1090
  • [48] An Optimal Algorithm for Allocation, Placement, and Delay Assignment of Adjustable Delay Buffers for Clock Skew Minimization in Multi-Voltage Mode Designs
    Lim, Kyuong-Hwan
    Kim, Taewhan
    2011 16TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2011,
  • [49] Power model analysis using variable rate clock network in CMOS processor
    Titus, T. Joby
    Vijayakumari, V.
    Saranya, B.
    Devi, V. S. Sanjana
    7TH INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATION AND NETWORKING TECHNOLOGIES (ICCCNT 2016), 2016,
  • [50] Design and Algorithm for Clock Gating and Flip-flop Co-optimization
    Yang, Giyoung
    Kim, Taewhan
    2018 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) DIGEST OF TECHNICAL PAPERS, 2018,
12345